This application relates to multiplexer circuits. More particularly, this application relates to time-balanced switching of multiplexer circuits.
Multiplexers are well-known circuits that accept N selector inputs and 2N data inputs, and generate a single data output. Each binary combination of the N selector inputs will select a corresponding data input and transmit its value to the data output. In general, each data input and data output can be a bus of M bits. For simplicity of illustration, the discussion herein will focus on a multiplexer with a single selector input, two single-bit data inputs, and one single-bit data output. However, it will be understood that the concepts discussed herein could easily be generalized to accommodate N selector inputs and 2N data inputs, where each data input and data output can include a bus of M bits.
A common problem of multiplexer circuits is that they often exhibit unbalanced switching times. That is, certain selector input transitions may result in faster output transitions than other selector input transitions. Such unbalanced switching times may result in clock signals with uneven duty cycles, cause significant problems in double data rate (“DDR”) data transmission, or otherwise degrade system integrity.
In view of the foregoing, it would be desirable to provide methods and apparatus for time-balanced multiplexer switching with respect to selector input transitions. Furthermore, it would be desirable to achieve such time-balanced switching with minimal changes to existing multiplexer implementations.